1. Field of the Invention
The present invention relates to a signal processing circuit, and more particularly to a signal processing circuit having an analog/digital conversion function for converting a signal from a signal source such as a photoelectric conversion unit into a digital signal.
2. Related Background Art
An amplification type image sensor is being studied and developed, in which photoelectrically excited carriers are amplified by active elements in a pixel unit. Such a photoelectric conversion device generally called a CMOS image sensor and various circuits such as logical circuits can be integrated on the same chip. Integration of an image sensor and an A/D converter and other circuits has been studied to date.
Integration of an image sensor and an A/D converter includes, for example, one A/D converter provided for each pixel, one A/D converter provided for each column, one A/D converter provided for the sensor output unit, or the like. Integration of one A/D converter for each column has been studied most vigorously.
The fundamental technology of a conventional A/D converter will be described with reference to FIG. 1. In the following, an A/D converter of the type that only one comparator is used and a conversion result is obtained while changing a reference voltage, will be described illustratively without using a relatively large scale parallel type such as a flash type and a two-step type.
An A/D converter is basically constituted of one comparator and one reference voltage generator.
A comparator 11 has a non-inverting input terminal 12 and an inverting input terminal 13. If an input to the non-inverting input terminal 12 is larger than an input to the inverting input terminal 13, a logical high level (usually a power source voltage) is output from a comparator output terminal 14, whereas if it is smaller, a logical low level (usually a GND level) is output.
In order to realize an A/D converter by using the comparator, a comparison reference voltage 15 is input to the inverting input terminal and a voltage 16 to be A/D converted is input to the non-inverting input terminal.
A comparison reference voltage generator unit outputs a ramp voltage which is synchronous with a digital counter and monotonously increases its amplitude, i.e., a derivative of the voltage with respect to time is always positive during each A/D conversion operation. A digital value is obtained from a count of the counter when an output of the comparator 11 is inverted.
In the case of a sequential comparison type, in accordance with an A/D conversion result obtained sequentially from the upper bit, the next reference voltage is determined and this operation is repeated.
If an output voltage from a photoelectric conversion element (e.g., a photodiode) is input to the non-inverting input terminal, the A/D converter converts input light into a digital signal.
The terms xe2x80x9cinvertingxe2x80x9d and xe2x80x9cnon-invertingxe2x80x9d are named after the output logic. There is no strict discrimination therebetween if only the transition of the output from the low level to the high level or vice versa is taken into consideration. In the following description, even if inverting is replaced by non-inverting, there is no practical problem. In this case, the logic of an encoder at the back stage may be changed or a protocol for processing the result after A/D conversion may be is changed.
Next, with reference to FIG. 2, the fundamental technology of an A/D converter used by a CMOS image sensor having one A/D converter per one column (hereinafter called a column A/D type CMOS sensor) will be described.
In an active pixel type sensor such as a CMOS sensor, generally a plurality of voltage sources, i.e., pixels, are connected in parallel to one common column 21. The amount of optically induced current of each pixel is too small and the generated voltage is insufficient for driving the column. To solve this, generally, an impedance conversion amplifier called a source follower is provided to supply its output to the column. The photoelectric conversion results of respective pixels are equivalently considered as voltage sources 22, 23 and 24. An output of each voltage source is selected by a corresponding one of select switches 25, 26 and 27 and supplied to the column to enable selective data read. Reference numeral 28 represents a constant current source for the source followers.
In the column A/D type CMOS sensor, a voltage selectively read in the above manner is supplied to a compartor 29 at which the voltage is compared with a reference voltage 30 to attain conversion.
The column A/D type CMOS operating on the basis of the above-described principle is associated with the following problems.
A first problem is concerned about consumption current. If an A/D converter is not provided for each column, the current consumed at each column is only current 28 for the source followers. In a column A/D type CMOS sensor, consumption current of the comparator (generally constituted mainly of a differential amplifier) 29 is required in addition to the consumption current by the source followers. A general image sensor has several hundred to several thousand columns. The total consumption power is therefore several hundred to several thousand times the consumption power of one column, and an increase in the consumption power cannot be neglected.
A second problem is concerned about a variation in gains of A/D converters. There is a variation in the conversion characteristics of A/D converters provided for columns. This variation appears as a differential non-linear error and an integration non-linear error which are caused by an offset voltage variation in initial stage differential amplifiers in A/D converters and a variation in performances of reference voltage generators, and the like. If the characteristics of A/D converters of respective columns are different, vertical fogged stripes are formed in an image and the image quality is degraded.
A third problem is concerned about a variation in input-output characteristics, particularly, amplification factors, of source followers. There is a general tendency that the gate length and width of a MOS transistor are shortened and narrowed in order to increase the integration degree. An image sensor has also this tendency. At such a high integration degree, there a variation in gains of source followers to be caused by variations of mutual conductances gm and differential source/drain resistances rds generated by a variation in manufacture processes. A variation in gains is several % at the most and a picked-up image is fogged.
FIG. 3 shows the structures of a conventional MOS type solid state image pickup device and an A/D converter for A/D converting an analog voltage signal of the image pickup device, and FIG. 4 is a timing chart illustrating the operation. A unit cell is constituted of a photodiode 81, an amplifying transistor 82, a select transistor 83 and a reset transistor 84.
A signal accumulated in a photodiode 81 (81-1-1, 81-1-2, . . . ) of each cell is amplified by an amplifying transistor 82 (82-1-1, 82-1-2, . . . ) and read out to a vertical signal line or detection node 88 (88-1, 88-2, . . . ) in the form of voltage. Since the amplifying transistor 82 and a load transistor 89 (89-1, 89-2, . . . ) form a source follower, a voltage corresponding to the signal in the photodiode 81 is read out to the vertical signal line 88. The MOS type solid image pickup device constructed as above is associated with a problem of fixed pattern noises corresponding to a variation in threshold voltages of amplifying transistors 82. Therefore, a noise canceling circuit is generally used, the operation of which will be described in the following.
By applying a pulse 501 to a select signal line 86-1, the row of the amplifying transistors 82-1-1, 82-1-2, . . . is activated. At this time, output signal voltages corresponding to the signals accumulated in the photodiodes 81-1-1, 81-1-2, . . . are read out to the vertical signal lines 88 (88-1, 88-2, . . . ). During the xe2x80x9cHxe2x80x9d level (pulse 501) activating the cells, an xe2x80x9cHxe2x80x9d voltage (pulse 502) is applied to a terminal 123 connected to the gate of a clamp transistor 91 to clamp the vertical signal line 95 (95-1, 95-2, . . . ) to a clamp voltage applied to a terminal 124.
Thereafter, an xe2x80x9cHxe2x80x9d voltage (pulse 503) is applied to a reset signal line 87 (87-1, 87-2, . . . ) to reset the voltage of the photodiode 81 (81-1-1, 81-1-2, . . . ). This reset voltage appears at the vertical signal line 88 and is transmitted via a clamp capacitor 90 (90-1, 90-2, . . . ) to a vertical signal line 95 (95-1, 95-2, . . . ). Next, a sample/hold transistor 92 (92-1, 92-2, . . . ) is turned on to transmit the signal to a vertical signal line 96 (96-1, 96-2, . . . ). Select pulses 505, 506, . . . are applied from a horizontal shift register 119 to horizontal select transistors 94 (94-1, 94-2, . . . ) to read out the signals of the selected row to a horizontal signal line 117.
A voltage signal read out to the horizontal signal line 117 is amplified by an output amplifier 120 and output to an A/D converter 121 at which the analog voltage signal is converted into a digital signal.
Since only one A/D converter 121 is used, it is required to perform a conversion operation at high speed. Problems of consumption power and noises are likely to occur. Since high speed conversion operation for outputs from a sensor having a number of pixels is required, its design becomes difficult.
FIG. 5 is a circuit diagram showing the outline of a conventional current output type CMOS sensor. In FIG. 5, reference numeral 131 represents a photodiode. An amplifying transistor 132 receives signal charges from the photodiode 131 and converts them into a current signal. Reference numeral 133 represents a reset switch, reference numeral 134 represents a sensor cell select switch, reference numeral 135 represents a horizontal select switch, and reference numeral 136 represents a fixed bias current source. A resistor 137 converts the signal current from the sensor cell into a voltage signal. A bias voltage source 139 determines a DC output level of an output amplifier 138.
Signal charges generated in the photodiode 131 are converted into a voltage by a capacitance of the gate of the amplifying transistor 132. In accordance with this converted voltage, the amplifying transistor 132 flows a drain signal current. When the switches 134 and 135 turn on, a difference between the current of the current source 136 and the output current of the amplifying transistor 132 appears at the resistor 137, and a voltage corresponding to this difference current appears at the output terminal of the output amplifier 138.
FIG. 6 is a circuit diagram showing the structure of an amplification type MOS solid state image pickup device of another current output type and its output read-out circuit. Reference numeral 1101 represents a photoelectric conversion unit. Signal charges generated in the photoelectric conversion unit 1101 are transmitted via a transfer transistor 1102 to the gate of an amplifying transistor 1103, and the signal charges are converted into a voltage signal at the gate. The amplifying transistor 1103 outputs a signal current Iout corresponding to the signal voltage to an output line via a pixel select transistor 1104. The output signal current is converted into a voltage by a resistor 1106 connected between the output terminal and inverting input terminal of a differential amplifier 1107. The converted voltage added to the voltage of a bias voltage source 1108 is output from the output terminal 1109. With the conventional circuits shown in FIGS. 5 and 6, as understood from the input voltagexe2x80x94output current characteristics of the amplifying transistor 1103 shown in FIG. 7, the output current is proportional to a square of an input voltage, and has the exponential characteristics of an input voltage equal to or smaller than the threshold voltage. The characteristics have therefore poor linearity and depend largely upon a temperature.
FIG. 8 is a circuit diagram of a conventional read circuit capable of suppressing noises caused by a manufacture variation of amplifying transistors 1103 of sensor cells. A current sample/hold circuit constituted of a switch 1108, a capacitor 1110 and a transistor 1112, holds an output current of an amplifying transistor 1103 in a reset state. Another current sample/hold circuit constituted of a switch 1109, a capacitor 1111 and a transistor 1113 holds a signal current output from the amplifying transistor 1103. The held currents are converted into voltages by current-voltage converter circuits 1116 and 1117, and a final output is obtained at an output terminal 1119 of a subtractor circuit 1118.
This conventional read circuit uses many transistors, switches, capacitors and amplifiers in order to suppress noises so that there are problems of a large consumption power and a large chip occupying area.
FIG. 9 is a circuit diagram in which a number of conventional photoelectric conversion units shown in FIG. 6 are disposed in parallel and image signals are output to common signal lines via pixel select switches. Signal charges in a photoelectric conversion element 201 (201-1, 201-2, . . . , 201-n) are converted into a voltage signal by the gate of an amplifying transistor 203 (203-1, 203-2, . . . , 203-n) and further converted into a current signal by the amplifying transistor 203. The current signal is output to a common signal line 209 via a pixel select transistor 204 (204-1, 204-2, . . . , 204-n), and again converted into a voltage signal by an amplifier 213 and a feedback resistor 212 to be thereafter output. Parasitic resistors r1 to rn of a wiring line from a high potential power source terminal are added between source terminals of the amplifying transistors. The more away from the power source terminal the pixel positions, the larger resistance as a sum of corresponding ones of rl to rn the pixel has. Even if the amounts of signal charges in photoelectric conversion elements 201 of pixels are the same and these signal charges are converted into the same voltage signal at the gates of the amplifying transistors 203, the output currents of the amplifying transistors 203 of pixels become different because of different parasitic resistor values added to the source terminals. The output current becomes smaller at the pixel positioned away from the power source terminal. This is so-called shading phenomenon. This phenomenon becomes more conspicuous as the output current of the amplifying transistor becomes larger. Generally, the output current becomes larger as the amount of signal charges in the photoelectric conversion unit becomes larger. A precision of an output voltage is lowered by the parasitic resistor.
Each pixel select switch 204 has parasitic capacitance 206 (206-1, 206-2, . . . , 206-n) called gate/drain overlap capacitance and parasitic capacitance 207 (207-1, 207-2, . . . , 207-n) called drain/well PN junction capacitance. A total sum of such parasitic capacitance of a sensor having a number of pixels becomes large. This capacitance functions as a load capacitance of the amplifier 213 shown in FIG. 9 so that there are problems of lower slew-rate and unstable phenomenon such as ringing.
In the conventional circuits described above, in order to convert signal charges in a photodiode into a voltage signal and to amplify this voltage signal which is then A/D converted while noises are canceled, many switching transistors and capacitors such as a clamp capacitor and a sample/hold capacitor are required. Problems of a large chip occupying area and an increased cost therefore arise. When voltage signals from selected vertical signal lines supplied to the horizontal signal line are sequentially converted by one A/D converter, it is necessary to perform a conversion process at very high speed. For example, a conversion process time as very short as several tens ns per one pixel is required for a sensor compatible with HD (High Definition). An expensive and high speed A/D converter is therefore necessary.
In the current output type CMOS sensor, the relation between an output current (Io) of the amplifying transistor 132 and a voltage signal generated from signal charges in the photodiode 131 shows the square characteristics as indicated by the following equation, and shows the exponential characteristics in the range of a small voltage signal, so that the linearity is poor:
Io=Kxc2x7W/L(Vs-Vth)2 
where K is a constant, W and L are the gate width and length of the amplifying transistor 132, and Vth is a threshold voltage.
An image pickup device having an A/D converter provided for each pixel is disclosed in JP-A-6-205307. This image pickup device compares an integrated pixel voltage with a reference voltage by a comparator to obtain AD data.
An image pickup device having an A/D converter provided for each column is disclosed in ISSCC 99 Session 17, PAPER WA 17.7 A, 250 mW, 600 Frames/s, 1280 xc3x97720 pixel 9b CMOS Digital Image Sensor. In this sensor, signals read out from each pixel column are compared with a reference voltage by a comparator to obtain digital data.
In the sensor disclosed in ISSCC 2000 Session 6, IMAGE Sensors PAPER MP 6.4 A 60 mW 10b CMOS Image Sensor with Column-to-Column FPN Reduction, a pixel signal is compared with a ramp signal to obtain AD data.
As above, in conventional circuits, a pixel signal is directly A/D converted or a pixel signal is A/D converted after it is amplified by an analog amplifier.
If a pixel signal picked up in the dark condition is to be directly A/D converted, a signal level is small relative to the rated input voltage of the A/D converter. Therefore, an S/N ratio becomes small and a quantization error of A/D conversion becomes large.
If a pixel signal is to be amplified by an analog amplifier to obtain large signal voltage, different amplification factors at respective columns generate vertical stripe noises on an image and the image quality is degraded considerably.
For a color image, the dynamic range of each color changes with a light source used for image pickup so that the full performance of an A/D converter cannot be utilized. For example, if the color temperature of a light source is low, a red pixel signal becomes large, whereas if the color temperature is high, a blue pixel signal becomes large, respectively limiting the input voltage to the A/D converter. The pixel size of an image pickup element is reducing year after year. If a pixel noise canceling circuit, an analog amplifier, a comparator, a D/A converter are to be provided for each column, the chip size becomes large. It is very difficult to design circuits to be disposed in the spaces between columns with the same circuit precision. These problems all result in vertical stripe noises on an image.
It is an object of the invention to provide a signal processing apparatus having an A/D converter capable of outputting a digital signal at a high precision.
In order to achieve the above object, one aspect of the invention provides a signal processing apparatus comprising: a plurality of circuit blocks each circuit block including a signal source and an output transistor adapted to receive a signal generated by the signal source at a control electrode region and outputting a corresponding signal from a main electrode region; and an analog/digital converter circuit adapted to sequentially process the signal from each of the plurality of circuit blocks, wherein the analog/digital converter circuit comprises a reference transistor for receiving a reference level at a control electrode region and outputting a corresponding signal from a main electrode region and a digital output circuit for outputting a digital signal in accordance with a signal output from the output transistor and a signal output from the reference transistor, and wherein the output transistor and reference transistor constitute an input unit of a differential amplifier circuit including the output transistor and reference transistor.
Another aspect of the invention provides a signal processing circuit comprising: a circuit block including a signal source and an output transistor adapted to receive a signal from the signal source at a control electrode region and output a corresponding signal from a first main electrode region; and an analog/digital converter circuit adapted to compare the signal output from the first control electrode region with a reference signal, control a level of a signal output from the first main electrode region of the output transistor in accordance with a comparison result, and output a digital signal in accordance with the comparison result.
Another aspect of the present invention provides a signal processing apparatus comprising: a plurality of pixels; and an analog/digital converter circuit adapted to output a digital signal in accordance with a comparison result between a level of a pixel signal from each of the pixels and a comparison reference level, wherein the analog/digital converter circuit changes relatively, within a variable range, the level of the pixel signal from each of the pixels and the comparison reference level, and changes the variable range.
In order to achieve the above object, another embodiment of the invention provides a signal processing apparatus comprising: a plurality of pixels disposed two-dimensionally; and a plurality of analog/digital converter circuits for converting signals output from the pixels into digital signals, wherein the plurality of analog/digital converter circuits are commonly provided for a plurality of columns.
Other objects and features of the present invention will become apparent from the following detailed description of embodiments when read in conjunction with the accompanying drawings.